During the American Physical Society (APS) March Meeting in Boston, researchers from Intel Labs demonstrated the progress they are making toward developing a commercially viable quantum computing system, including breakthroughs in hardware and software development for the quantum computing stack and development of a tool that will rapidly speed the research and optimization of silicon spin qubit technologies. Since establishing its collaborative research program with QuTech in 2015, Intel has been driving research to realize the promise of quantum computing, delivering advancements spanning the entire quantum stack — from qubit devices to the hardware and software architecture required to control these devices as well as quantum applications.
More: Intel Labs | Quantum Computing at Intel
Mode Hybridization Analysis of Bus Resonators for a Superconducting Multi-Qubit Chip
Presentation Details: 10:12-10:24 a.m. EST, Monday, March 4, 2019, Session A42: Multi-Qubit Characterizations and Cross-talk for Superconducting Qubits, Room: 201A
Abstract: Researchers present an effective numerical method to analyze the mode hybridization in a superconducting multi-qubit chip. Surface code, a promising architecture for fault-tolerant quantum computing, requires qubits with connectivity to all nearest neighbors. This extensive interconnectivity together with a strong coupling coefficient among the qubits and resonators causes mode hybridization. A complete analysis of the chip is needed in these conditions to accurately predict the loaded frequency of the bus resonators and thereby also the gate time. We present and experimentally verify a simulation method for analyzing the complete chip where finite-element electromagnetic simulation is combined with a numerical circuit simulation for accurate and fast computation.
Authors: Nadia Haider (QuTech and Netherlands Organisation for Scientific Research (TNO), Delft, The Netherlands); Jonathan Gnanadhas (QuTech, Netherlands Organisation for Applied Scientific Research (TNO) and Delft University of Technology, Delft, The Netherlands); Marc Beekman (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); Rene Vollmer (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); Nandini Muthusubramanian (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); Roman Caudillo (Intel); Alessandro Bruno (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); David Michalak (Intel); Filip Malinowski (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); Cornelis Christiaan Bultink (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands); Adel A Elsherbini (Intel); Lester Lampert (Intel); Alexander Yarovoy (Microwave Sensing, Signals and Systems, Delft University of Technology, Delft, The Netherlands); Jim Clarke (Intel) Leonardo DiCarlo (QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands)
Presentation Details:11:15-11:51 a.m. EST, Monday, March 4, 2019, Session B35: Silicon Spin Qubits, Room: 205B
Abstract: Intel is developing a 300mm process line for spin qubit devices using state-of-the-art immersion lithography and isotopically pure epitaxial silicon layers. Both Si-MOS and Si/SiGe devices are being evaluated in this multi-layer integration scheme. In this talk, researchers will be sharing current progress toward spin qubits starting with substrate characterization. Transistors and quantum dot devices are then co-fabricated on the same wafer and allow calibration to Intel’s internal transistor processes. Electrical characterization and feedback is accomplished through wafer scale testing at both room temperature and 1.6K prior to milli-kelvin testing. Accelerated testing across a 300mm wafer provides a vast amount of data that can be used for continuous improvement in both performance and variability. This removes one of the bottlenecks toward a large-scale system: trying to deliver an exponentially fast compute technology with a slow and linear characterization scheme using only dilution refrigerators.
Author: Jim Clarke (Intel)
A Quantum Solution for Efficient Use of Symmetries in Exact Diagonalization of Many-Body Systems
Presentation Details: 9-9:12 a.m. EST, Wednesday, March 6, 2019, Session K42: Applications of Noisy Intermediate Scale Quantum Computers IV, Room: 201A
Abstract: The use of symmetries allows the block-diagonalization of the Hamiltonian of a many-body system, allowing it to be expressed in terms of symmetry-adapted basis states. The problem of finding the group representatives of these basis states and their corresponding symmetries is currently a memory/computational bottleneck on classical computers. We apply Grover’s search in the form of a minimization procedure to solve this problem, improving upon the existing technique present in the literature to reduce the number of qubits and oracle calls. Our quantum solution provides an exponential reduction in computational memory, and a quadratic speedup in time. We discuss explicitly the full circuit implementation of Grover minimization as applied to this problem, finding that the oracle only scales as poly-log in the size of the search space. Further, we design an error mitigation scheme that significantly reduces the effects of noise on the computation, showing how it can be run in the Noisy Intermediate Scale Quantum era.
Authors: Albert Schmitz (University of Colorado, Boulder); Sonika Johri (Intel)
Impact of Qubit Connectivity on Quantum Algorithm Performance
Presentation Details: 1:27-1:39 p.m. EST, Wednesday, March 6, 2019, Session L28: Distributed Quantum Computation, Networking and Information Security, Room: 161
Abstract: Quantum computing hardware is undergoing rapid development from proof-of-principle devices to scalable machines that could eventually challenge classical supercomputers on specific tasks. On platforms with local connectivity, the transition from one- to two-dimensional arrays of qubits is seen as a natural technological step to increase the density of computing power and to reduce the routing cost of limited connectivity. Here researchers map and schedule representative algorithmic workloads – the Quantum Fourier Transform (QFT) relevant to factoring, the Grover diffusion operator relevant to quantum search, and Jordan-Wigner parity rotations relevant to simulations of quantum chemistry and materials science – to qubit arrays with varying connectivity. In particular, we investigate the impact of restricting the ideal all-to-all connectivity to a square grid, a ladder and a linear array of qubits. Our schedule for the QFT on a ladder results in running time close to that of a system with all-to-all connectivity. Our results suggest that some common quantum algorithm primitives can be optimized to have execution times on systems with limited connectivities, such as a ladder and linear array, that are competitive with systems that have all-to-all connectivity.
Authors: Adam Holmes (Intel); Sonika Johri (Intel); Gian Giacomo Guerreschi (Intel); Jim Clarke (Intel); Anne Matsuura (Intel)
Full 300mm Fin Based QD Device Characterization
Presentation Details: 2:30-2:42 p.m. EST, Wednesday, March 6, 2019, Session P29: Semiconducting QC Architectures and Quantum Photonics, Room 162A
Abstract: Intel’s efforts toward the fabrication of spin qubit devices have required a comprehensive device characterization, from transistors and quantum dots, to qubits, which have been co-fabricated in the same die/wafer. In this talk, researchers present an in-depth device characterization, and the results from quantum dot devices manufactured in a full 300mm line. We will give details of the fin based process flow, which yields high-charging energy devices (>35meV). The extraction of QD related figures of merit from room and low temperature testing (1.6K) are part of the method to rapidly screen 300mm wafers with thousands of devices that are used to determine the spin qubit devices that will be taken to the milli-kelvin measurements; keeping up with the pace of the 300mm fab output.
Authors: Hubert C George (Intel); Nicole Thomas (Intel); Ravi Pillarisetty (Intel); Lester Lampert (Intel); Thomas Watson (Intel); Jeanette Marie Roberts (Intel); Stephanie Bojarski (Intel); Payam Amin (Intel); Jessica Torres (Intel); Matthew Metz (Intel); Guoji Zheng (QuTech and Kavli Institute of Nanoscience, TU Delft); Anne-Marije Zwerver (QuTech and Kavli Institute of Nanoscience, TU Delft); Jelmer Boter (QuTech and Kavli Institute of Nanoscience, TU Delft); Juan Pablo Dehollain (QuTech and Kavli Institute of Nanoscience, TU Delft); GertJan Eenink (QuTech and Kavli Institute of Nanoscience, TU Delft); Leonardo Massa (QuTech and Kavli Institute of Nanoscience, TU Delft); Diego Sabbagh (QuTech and Kavli Institute of Nanoscience, TU Delft); Nodar Samkharadze (QuTech and Kavli Institute of Nanoscience, TU Delft); Christian Volk (QuTech and Kavli Institute of Nanoscience, TU Delft); Brian Paquelet Wütz (QuTech and Kavli Institute of Nanoscience, TU Delft); Menno Veldhorst (QuTech and Kavli Institute of Nanoscience, TU Delft); Giordano Scappucci (QuTech and Kavli Institute of Nanoscience, TU Delft); Lieven Vandersypen (QuTech and Kavli Institute of Nanoscience, TU Delft); Jim Clarke (Intel)
Intel Superconducting Qubits, Part 1: Performance Improvements towards Enabling Quantum Applications
Presentation Details: 1:39-1:51 p.m. EST, Thursday, March 7, 2019, Session S35: 3D Integration for Superconducting Qubits, Room: 205B
Abstract: Quantum processors based on superconducting materials with flux-tunable transmon qubits present many challenges, including minimizing flux and microwave xtalk, improving qubit frequency targeting, extending T1/T2 times, and ultimately maximizing gate fidelities. Here we present our fabrication capabilities addressing some of these challenges with die sizes ranging from small laterally wire-bonded 2-qubit chips to larger flip-chip BGA-bonded 7-qubit and 17-qubit chips. Through improved die processing, including improvements to materials interfaces, integration of air bridges, and Josephson Junction fabrication improvements, we demonstrate low flux and microwave cross talk and qubit performance improvements resulting in 1Q and 2Q gate fidelities that enable algorithm exploration and execution.
Authors: Roman Caudillo (Intel); David Michalak (Intel); Lester Lampert (Intel); Adel A Elsherbini (Intel); Javier A Falcon (Intel); Ye Seul Ashley Nam (Intel); Preston T Myers (Intel); Sonika Johri (Intel); Xiang Chris Zou (Intel); Jeanette Marie Roberts (Intel); Alessandro Bruno (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Nandini Muthusubramanian (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Cornelis Christiaan Bultink (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Filip Malinowski (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Nadia Haider (QuTech and TNO); Leonardo DiCarlo (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Jim Clarke (Intel)
Intel Superconducting Qubits, Part 2: Integration on Through-Silicon-Via (TSV) Substrates
Presentation Details: 1:51-2:03 p.m. EST, Thursday, March 7, 2019, Session S35: 3D Integration for Superconducting Qubits, Room: 205 B
Abstract: Quantum computing holds the potential for significantly improving computing speed relative to classical computing for selected algorithms and applications. Many researchers using the transmon-style of circuit QED are producing chips with ever-increasing numbers of qubits. While higher numbers of qubits can increase the usefulness of algorithms that can be performed, the increase in chip size correspondingly shifts cavity and drum modes into a range where the qubits could be adversely affected. One solution is to implement through-silicon-vias (TSVs) and chip/cavity fuzz buttons to supply more ground connections. We present recent microwave modeling and fabrication results on “flip-chips” containing TSVs for grounding and a ball-grid array die-package interface for electrical signals.
Authors: David Michalak (Intel); Roman Caudillo (Intel); Lester Lampert (Intel); Adel A Elsherbini (Intel); Javier A Falcon (Intel); Ye Seul Ashley Nam (Intel); Preston T Myers (Intel); Jeanette Marie Roberts (Intel); Alessandro Bruno (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Nandini Muthusubramanian (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Cornelis Christiaan Bultink (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Filip Malinowski (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Nadia Haider (QuTech and TNO); Leonardo DiCarlo (QuTech and Kavli Institute of Nanoscience, Delft University of Technology); Jim Clarke (Intel)